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地址：深圳市宝安区西乡街道桃源居7区15栋1单元801
产品名称：
台湾IOI FWBX2-PCIE1XE220图像4路采集卡LSI FW643 1394B视觉全新现货
台湾1394B四路图像采集卡FWBX2-PCIE1XE220采集卡非常适合AOI、3D SPI和3D检测、印刷检测、平板显示器或玻璃检测等使用。
台湾IOI 1394B 800M采集卡FWBX4-PCIE4XE120
4路1394B接口PCI-E4X，4路实时
Host Adapters
FWBX4-PCIE4XE120
Quad OHCI IEEE 1394b (Firewire 800) to PCI Express x4 Gen2 Host Card
Highlights |
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Introduction |
The FWBX4-PCIE4XE120 is a Quad OHCI IEEE 1394b (Firewire 800) to PCI Express x4 Gen2 Host Card. FWBX4-PCIE4XE120 is designed with two key components.
MultipleVCs (Virtual Channels) on the PCI Express link provide native support for QoS (Quality of Service) transmission for real-time multimedia applications in a standards-based framework, ensuring compatibility with current future operating systems. Active-state power management allows dynamic power management during periods of reduced network activity. |
Technical Specifications |
| PCI Express:Standards complianto PCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0)o PCI Express Base Specification, Revision 2.0 Erratao Backward-compatible with the PCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1) PCI Express Base Specification, Revision 1.0a (PCI Express Base r1.0a)o PCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2)o Microsoft Vista®-complianto Supports Access Control Serviceso Dynamic Link-width controlo Dynamic SerDes speed controlNote: Additional specifications, with which this product complies, are listed in Supplemental Documentation.High Performanceo Non-Blocking Internal architectureo Full line rate on all Portso Cut-Thru latency – 190 ns for Link widths of x4 to x1o Maximum payload size set to 256 128performancePAKTMo Read PacingTM (intelligent bandwidth allocation)o Dual CastTMo Dynamic Buffer Pool Architecture for faster credit updatesPCI Express Power Managemento Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready, L3 (with Vaux supported)o Conventional PCI-compatible Device Power Management states – D0 D3hoto Active State Power Management (ASPM)Quality of Service (QoS) supporto Two Virtual Channels (VC0 VC1) per Porto Eight Traffic Classes (TC[7:0]) per Porto Weighted Round-Robin (WRR) Port Virtual Channel (VC) arbitrationOHCI (Open Host Controller Interface)Enhanced with the OHCI 1.2 draft specification for 1394b-2002 PHY full operational compliance.OHCI 1.0 backwards compatible. Configurable via EEPROM to operate in either OHCI 1.0 OHCI 1.1 mode.8 Kbyte isochronous transmit FIFO.4 Kbyte asynchronous transmit FIFO.8 Kbyte isochronous receive FIFO.8 Kbyte asynchronous receive FIFO.Dedicated asynchronous isochronous descriptor-based DMA engines.Eight isochronous transmit contexts.Eight isochronous receive contexts.Supports parallel processing of incoming physical read write requests.Supports up to 48-bit addressing per OHCI specification for the physical DMA transfers.1394b-2002 LinkSupport for calculation checking of the cyclic redundancy check (CRC) on outgoing incoming packetsSupport for decoding the destination ID of incoming 1394 packets to determine if an acknowledge is needed.Cycle isochronous resource manager capabilitySupport for 1394a-2000 1394b acceleration features1394b-2002 PHYIEEE 1394b-2002 compliant ports supporting 1394b speeds of 800 Mb/s 400 Mb/s while maintaining backward compatibility to IEEE 1394a-2000 speeds of 100 Mb/s, 200 Mb/s, 400 Mb/s over 4.5 m copper.Full support for IEEE 1394a-2000 1394-1995 standard provisions for high-performance serial bus.Registers to indicate power class modes.Extended BIASHANDSHAKE time for enhanced interoperability with camcorders.While unpowered connected to the bus, the device does drive TPBIAS on a connected port even if receiving incoming bias voltage on that port.No need for an external filter capacitor for PLL.Link-on as a part of the internal PHY core-link interface.Arbitrated short bus reset.Ack-accelerated arbitration fly-by concatenation.Connection debounce.Multispeed packet concatenation.PHY pinging remote PHY access packets.Port disable/suspend/resume.PHY-link interface initialization reset.Support for the 1394a-2000 register set.Fully interoperable with FireWire® i.LINK® implementation of IEEE 1394-1995.Cable power fail interrupt reported when voltage at TPCPS pin falls below 7.5 V.Separate cable bias driver termination voltage supply for each port provided.Number of Ports:Four External Bilingual ports with Screw Holes for thumbscrew locking Type 1394b Cableo OHCI 4: One 1394b Bilingual porto OHCI 3: One 1394b Bilingual porto OHCI 2: One 1394b Bilingual porto OHCI 1: One 1394b Bilingual portBus Power Connector:Either Big IDE 4-pin DC Power Connector / SATA 15pin Power Connector |
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Operating System Requirements |
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159-1998-9936
联系人：邓女士
Q Q ：1455046925
传真：0755-61119959
地址：深圳市宝安区西乡街道桃源居7区15栋1单元801
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